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| HSP45116-DB USER'S MANUAL May 1999 File Number 3367.3 HSP45116 Daughter Board The HSP45116-DB is a daughter board designed to mate with the HSP-EVAL for rapid evaluation and prototyping of the HSP45116 Numerically Controlled Oscillator Modulator. Together, the board set provides a mechanism to evaluate HSP45116 operation using IBM PCTM based I/O and control. As shown in Figure 1, the HSP45116-DB maps the input, output, and control signals of the HSP45116 to three 50 pin headers. These headers mate with connectors on board the HSP-EVAL to interface the HSP45116's various I/O and control signals with the HSP-EVAL's data busses. This interface establishes a path for PCTM based I/O and control of the HSP45116-DB via the HSP-EVAL. An IBM PCTM based software package is supplied which controls operation to the HSP45116-DB/HSP-EVAL board set. The software package provides the user with a DOS command line interface and graphical user interface for daughter board I/O and control. Since the software supports data acquisition from the HSP45116, software based signal analysis may be used to quantify part performance. The degree of control exerted by the software varies depending upon the clock supplied to the HSP45116-DB. If a high speed clock is supplied via the HSP-EVAL's on board oscillator or external clock pin, the software can be used to exert real time control. If a software controlled clock is provided, the HSP45116-DB can be driven with a user defined data set, while storing results back to the PC for later analysis. The HSP45116-DB is a 6 layer printed circuit board which comes populated with one HSP45116GC-25. The PC based software required to control the daughter board via the HSP-EVAL is also provided. Features * Designed for Use with HSP-EVAL * Access to HSP45116s Input, Output, and Control Signals Through Three 50 Pin Headers * HSP45116 Control Signal States May be Set Through Hardware Configuration or Software * Two Separate Software Packages for Daughter Board I/O and Control * High Speed I/O Supported Applications * PC Based Performance Analysis of HSP45116 When Used with HSP-EVAL HSP45116 Daughter Board 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 IBM PCTM is trademark of IBM Corporation. HSP45116-DB Getting Started This section describes the initial evaluation system setup for the HSP45116-DB and HSP-EVAL board set. The system setup consists of mother/daughter board assembly, software installation, and system test to verify proper operation of the board set. System Requirements for the Evaluation Board Software The PC system targeted to run the HSP45116-DB software (NCOM-SOFT) and interface with the evaluation board set must meet the following requirements: - IBM PC/XT/AT, PS/2, or 100% compatible with a minimum of 640K of random access memory (RAM) (NCOM-SOFT does not require extended memory) - At least 200kB of free disk space on your hard disk - DOS Version 3.0 or higher - One parallel port with 27 Pin D-Sub connector Assembly The evaluation board set is assembled by mating the HSP45116-DB daughter board with the HSP-EVAL motherboard. This is accomplished by inserting the header pins sticking through the bottom (solder side) of the daughter board into the three 2 x 25 pin connectors on the motherboard. Proper alignment requires that the J1, J2, and J3 headers on the HSP45116-DB mate with the J1, J2, and J3 connectors on the HSP-EVAL. A moderate amount of force is required to seat the header pins in the motherboard connectors. Software Installation The distribution diskette contains a program called INSTALL.EXE which installs the NCOM-SOFT software onto the target hard disk. Note: The steps in this section assume you are installing NCOM-SOFT from a diskette in drive A: onto a hard drive C:. If a different configuration is used, substitute the letter of the drive where the diskette is located for drive A;. Substitute the letter for the hard drive for drive C: EXT_CLK OSC_CL CTL0 OE_BUS1 OE_BUS2 OE_BUS3 OECTLLO OECTLHI ADDR0 OUTPUT ENABLE JUMPERS CLOCK SELECT JUMPERS CONFIGURATION JUMPER FIELD A 50 PIN CONTROL HEADER (J2) CONFIGURATION JUMPER FIELD B 50 PIN OUTPUT HEADER (J3) 50 PIN INPUT HEADER (J1) CONTROL CLK RIN0-15 16 RO0-15 16 IMIN0-15 16 HSP45116 IO0-15 16 HSP45116-DB FIGURE 1. HSP45116-DB BLOCK DIAGRAM ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 STAT0 STAT1 DEFAULT JUMPER PLACEMENT INDICATOR STAT2 STAT3 PCRD0 PCRD1 SR_RD N.C. N.C. OUTPUT SELECT JUMPERS BOARD ADDRESS JUMPERS As part of the initial assembly, the HSP-EVAL and HSP45116DB must be provided with the default jumper configuration to ensure proper operation with the system test software. Each board leaving the factory is supplied with the default configuration, but the respective configurations are examined here for completeness. The motherboard's default configuration is realized by inserting jumpers into the HSP EVAL's J4 jumper field as shown in Figure 2 (see the HSP-EVAL User's Manual for more detailed information). The default configuration for the HSP45116-DB requires jumper placement across the Configuration Jumper Fields A and B and the J3 Control Header as shown in Table 1. Before using the board set with the supplied software, power must be supplied to the boards, and the HSP-EVAL must be connected to the parallel port of the target PC. Power is provided to the boards by connecting the VCC and GND pins of the J6 header on the HSP-EVAL to a standard 5V 5% supply. As an alternative, power may be supplied through the HSPEVAL's 96-Pin DIN connectors. The HSP-EVAL is connected to the target PC by connecting the HSP-EVAL's 26-PIN shrouded header to the PC's parallel port using the supplied ribbon cable. FIGURE 2. CONFIGURATION JUMPER FIELD J4 2 HSP45116-DB TABLE 1. OVERLAY OF DEFAULT JUMPER CONFIGURATION ONTO THE SIGNAL MAPPING FOR THE J3 CONTROL HEARDER AND THE CONFIGURATION JUMPER FIELDS A AND B PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 JA SIGNAL MNEMONIC CLKOUT BUF_OUT GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND SA SIGNAL MNEMONIC BUF_IN CLK_IN PULL UP PULL UP N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. PULL UP ENTIREG ENI CLROFR LOAD PMSEL AD1 MUX0 MUX1 PACI PEAK RBYTILD MODPI/2PI J3A SIGNAL MNEMONIC N.C. C0 C2 C4 C6 GND C9 C11 C13 C15 N.C. CTL1 CTL3 CTL5 CTL7 CTL8 CTL10 CTL12 CTL14 GND GND GND GND GND GND J3B SIGNAL MNEMONIC GND C1 C3 C5 C7 C8 C10 C12 C14 GND N.C. CT2 CTL4 CTL6 GND CTL9 CTL11 CTL13 CTL15 N.C. N.C. N.C. N.C. N.C. N.C. SB SIGNAL MNEMONIC N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. ENPHREG ENOFREG N.C. ENCFREG BINFMT AD0 WR N.C. N.C. ACC N.C. MOD0 MOD1 JB SIGNAL MNEMONIC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 JUMPER CONFIGURATION FIELD A J3 CONTROL HEADER JUMPER CONFIGURATION FIELD B To start the installation program: Make sure computer is on and the DOS prompt is displayed. Type: C: Create a subdirectory to contain the NCOM-SOFT Programs by typing: MD \NCOMSOFT The INSTALL program downloads the NCOM-SOFT programs, NCOMCTRL and NCOM_CMD, to the NCOMSOFT subdirectory on the target hard drive. In addition, a subdirectory called NCOM_CHK is created into which files used to perform functional verification are downloaded. Modifications to AUTOEXEC.BAT To run the NCOM-SOFT programs, DOS must be able to find the executable files. To ensure that DOS can always find the NCOM-SOFT executables, modify the search path to include the location of the NCOM-SOFT directory. For example, if the NCOM-SOFT programs are installed on drive C: in a subdirectory called \NCOMSOFT, add the following 3 HSP45116-DB line to the end of the existing Path command in the AUTOEXEC.BAT file: ;C:\NCOMSOFT If your AUTOEXEC.BAT file does not contain a PATH command, add the following command to the file: PATH=C:\NCOMSOFT Reboot the PC so that the search path changes will take effect. HSP45116-DB Control Panel Software The HSP45116-DB Control Panel is a graphical user interface for controlling the operation of the HSPEVAL/HSP45116-DB Board Set via an IBM PC or compatible. The control panel, as shown in Figure 3, supports loading the HSP45116's frequency, phase, and timer accumulator configuration registers, as well as setting the state of various control inputs. In addition, the control panel is used to specify files which serve as a data source for the HSP45116's RIN0-15 and IMIN0-15 inputs and a data sink for the RO0-15 and IO0-15 outputs. Operation of the control panel software is dependent on the clock source provided to the HSP45116-DB as specified in the clock select portion of the control panel. The HSP45116-DB Control Panel is invoked by typing: NCOMCTRL System Test Test software is provided to verify operation of the HSPEVAL and HSP45116-DB board set. Prior to performing the system test, it is assumed that the evaluation board set has been assembled and configured as described above; power has been applied to the board set, and the 26-Pin shrouded header on board the HSP-EVAL has been connected to the parallel port of the target PC via the supplied cable. The system test is initiated by the following: Change the current directory to that which contains the software required for the system test by typing CD C:\NCOMSOFT\NCOM_CHK Port Configuration Communication between the Control Panel software and the evaluation board set requires that the software knows which of the PC's parallel ports is being used for communication with the HSP-EVAL and which board address the HSP-EVAL has been configured for. The default configuration assumes that LPT1 is being used and the HSP-EVAL has been configured for a board address of 0. The Port Configuration can be inspected by opening up the port configuration window using the F9 function key. As shown in Figure 4, the window displays the available parallel ports and their addresses. Also displayed are the current port and HSP-EVAL Board address being used by the Control Panel software. 4 HSP45116-DB HSP45116-DB CONTROL PANEL CLOCK SELECT MANUAL CLK PORT CLK OSC. CLK EXTERNAL CLKA FILE I/O SELECT INPUT FILE: INPUT.DAT OUTPUT FILE: OUTPUT.DAT CONTROL SIGNALS 0 0 1 1 1 ENPHREG CLROFR LOAD BINFMT PMSEL (RINO-15) (IMINO-15) 7FFF 0000 HSP45116 NCOM 0000 0000 (RO0-15) (IO0-15) CLOCK NUMBER 0 CENTER FREQUENCY REGISTER OFFSET FREQUENCY REGISTER 40000000 00000000 PHASE OFFSET REGISTER TIME ACCUMULATOR REGISTER 0000 00000000 F1 - HELP F2 - START CLOCK F0 - PORT CONFIG F10 - QUIT FIGURE 3. CONTROL PANEL SCREEN AS DISPLAYED ON PC HSP45116-DB CONTROL PANEL CLOCK SELECT MANUAL CLK PORT CLK OSC. CLK EXTERNAL CLKA FILE I/O SELECT PORT CONFIGURATION INPUT FILE: 1MHZCMP OUTPUT FILE: UPCNVRTI AVAILABLE PRINTER PORTS ADDRESS (HEX) LPT1 CONTROL SIGNALS 0 0 1 1 1 ENPHREG# CLROFR# LOAD # BINFMT# PMSEL LPT2 LPT3 CURRENT PORT SELECTION : CURRENT HSP-EVAL ADDRESS : LPT1 0 0x3BC 0x378 0x3BC 0-15) 0-15) CENTER FR OFFSET FREQ 000 00000000 F1 - HELP ESC - RETURN F10 - QUIT FIGURE 4. PORT CONFIGURATION WINDOW AS DISPLAYED ON PC 5 HSP45116-DB The current port and HSP-EVAL address are changed by opening up the Port Configuration Window, using the up/down arrow keys to select the desired parameter, and toggling the space bar to change the selection. Proper operation of the control panel software requires that the HSP-EVAL Board address specified in the port configuration window matches the address jumpered in the Address Selection Section of the HSP-EVAL's J4 jumper field (see HSP-EVAL User's Manual). the software does not support file based I/O to the evaluation board set since the data rate required may be much greater than that capable through the parallel port of the PC. In this mode, the Control Panel disables file based I/O and the display of NCOM output. The clocking mode used by the control panel is indicated by the position of the "check mark" symbol within the Clock Select portion of the Control Panel. A different clocking mode may be selected by positioning the "check mark" symbol in front of the desired clocking mode. The position of the "check mark" is changed by using the cursor keys to move the active window to the desired position and then toggling the space bar to move the "check mark". Clock Select The Clock Select portion of the control panel is used to tell the Control Panel software which of four different clock sources is being supplied to the HSP45116-DB. The choices include one of two different software generated clocks (Manual CLK or Port CLK), an oscillator clock provided by the HSP-EVAL (OSC. CLK), or an externally supplied clock (External CLK). The clock mode selected must be consistent with the Clock Select jumper position in the HSP-EVAL's J4 jumper field. If either Manual CLK or Port CLK are specified in the Control Panel, the clock select jumper must be inserted in the CTL0 position. If either OSC. CLK or External CLK is specified, the jumper must be inserted at the OSC_CLK or EXT_CLK position respectively. In Manual CLK mode, single clock pulses are sent to the HSP45116 by depressing the F2 function key. The clock pulse is software generated by setting and clearing the CTL0 bit of the CTL Control Register on the HSP-EVAL. After each clock, the HSP45116-DB's RO0-15 and IO0-15 outputs are serialized and read into the PC for display in the Control Panel. In this mode, file input and output is supported (see File I/O Select Section). In Port CLK mode, a free running clock is sent to the HSP45116 by depressing the F2 function key. The clock pulses are software generated by continually setting and clearing the CTL0 bit of the CTL0-15 Register on the HSPEVAL. After each clock the HSP45116-DB's RO0-15 and IO0-15 outputs are serialized and read into the PC for display in the Control Panel. In this mode, file input and output is supported (See File I/O Select Section). In OSC. CLK mode, the HSP45116 is supplied with a clock by the oscillator on-board the HSP-EVAL. In this mode, the Control Panel can be used for modifying the various control signal states, the configuration registers, and the complex inputs to the NCOM. However, the software is unable to provide file based I/O to the evaluation board set since the data rate required by the oscillator clock is orders of magnitude greater than that possible through the parallel port of the PC. As a result, the Control Panel disables file based I/O and the display of NCOM output in this mode. In External CLK mode, the HSP45116 is supplied with a clock through the 96-Pin DIN connector P1 on the HSPEVAL. In this mode, the Control Panel can be used for modifying control signal states, the various configuration registers, and the complex inputs to the NCOM. However, File I/O Select The File I/O Select portion of the Control Panel allows the user to specify files which can be used as an input data source or an output data sink for the HSP45116-DB. If file based input is selected, Control Panel software down loads data from the specified file to registers on the HSP-EVAL and clocks the data into the RIN0-15 and IMIN0-15 inputs of the HSP45116. If file based output is specified, the software reads the data on the RO0-15 and IO0-15 outputs of the HSP45116 via the HSP-EVAL's output shift register and stores the data in the specified file. The input data is loaded on to the input busses prior to the software generated clock and the output data is read from the output busses following the software generated clock. File based I/O is activated by using the space bar to toggle the "check mark" symbol in the window proceeding the Input and Output File identifier in the Control Panel's File I/O Section. If either file input or output is activated, the respective file name must be entered in the window to the right of the I/O file identifier. File input or output may be disabled at any time by toggling the respective "check mark". Note: file I/O is only valid when either the `Manual CLK' or `Port CLK' clocking modes are selected and it is disabled if other clocking modes are specified. The input and output data files are ASCII based and have a format as described in Appendix A. There is no limitation to the input and output file size, and care must be taken if file output is specified since data is collected in the file until file output is deactivated or the NCOMCTRL Program is exited. HSP45116 Complex Data Inputs The data windows to the left of the HSP45116 icon are used to specify hexadecimal values which drive the part's complex inputs, RIN0-15 and IMIN0-15. Data entered into these windows is down loaded to registers on the HSP-EVAL which drive the HSP45116-DB's complex input busses. Note: Jumpers must be inserted into the OE_BUS1 and OE_BUS2 positions of the HSP-EVAL's J4 jumper field to enable the register outputs containing the complex data. 6 HSP45116-DB The complex inputs may be changed by entering hexadecimal values into the data windows. The contents of a particular data window may be edited by depressing the Control Signals The Control Signal portion of the control panel is used to define the state of various control signal inputs to the HSP45116. The logical state of a control signal is set by using the space bar to toggle the signal state in the window preceding the specified control signal. For the control signal states displayed in the Control Panel to be active at the HSP45116, the respective control signals must be jumpered to the HSPEVAL's CTL0-15 Bus via the HSP45116-DB's J3 jumper field as shown in the default jumper configuration displayed in Table 1 (see Jumper Configuration Section). The Control Signal descriptions are contained in the HSP45116 Data Sheet. Help Help windows are provided as a source of information for control panel usage. The help window is activated by the F1 function key, and contains information based on the current active data window. Configuration Registers The bottom of the control panel displays four data windows which contain the hexadecimal values loaded into the HSP45116's Center Frequency, Offset Frequency, Phase Offset, and Time Accumulator Registers. The contents of a particular configuration register may be updated by entering a new hexadecimal value into the data window. The current value in a window may also be edited by depressing the Command Line Interface As an alternative to the control panel, a command line interface is provided which allows the user to control the HSP45116-DB by issuing commands from the DOS prompt. The commands perform basic I/O and configuration functions by up or down loading data to the HSP45116 through the HSP-EVAL. The Command Line program has the following usage: NCOM_CMD [Command] [ARG 1] [ARG 2] TABLE 2. COMMAND LIST FOR COMMAND LINE INTERFACE SOFTWARE COMMAND CF OF TI PO CL RI II ARGUMENT #1 32-BIT HEXADECIMAL VALUE 32-BIT HEXADECIMAL VALUE 32-BIT HEXADECIMAL VALUE 16-BIT HEXADECIMAL VALUE 16-BIT HEXADECIMAL VALUE 16-BIT HEXADECIMAL VALUE 16-BIT HEXADECIMAL VALUE ARGUMENT #2 COMMAND DESCRIPTION Loads HSP45116's Center Frequency Register with hexadecimal value specified in Argument #1. See Notes 1 and 2. Loads HSP45116's Offset Frequency Register with hexadecimal value specified in Argument #1. See Notes 1 and 2. Loads HSP45116's Time Accumulator Register with hexadecimal value specified in Argument #1. See Notes 1 and 2. Loads HSP45116's Phase Input Register with hexadecimal value specified in Argument #1. See Note 2. Loads the HSP-EVAL's CTL Control Register with the 16-bit value specified in Argument #1. Loads the specified Hex value into the HSP-EVAL Register (Input Register #2) driving the Real Input bus (RIN0-15) Of The HSP45116-DB. See Note 3. Loads The Specified Hex Value Into The HSP-EVAL Register (Input Register #1) driving the imaginary Input Bus (IMIN0-15) Of The HSP45116-DB. See Note 3. 7 HSP45116-DB TABLE 2. COMMAND LIST FOR COMMAND LINE INTERFACE SOFTWARE (Continued) COMMAND PF ARGUMENT #1 INPUT FILE ARGUMENT #2 OUTPUT FILE COMMAND DESCRIPTION Down loads complex samples stored in the file specified by Argument #1 into the HSP-EVAL Registers driving the Real and Imaginary Input Buses of the HSP45116-DB, clocks the data into the part, and stores the complex output to the file specified by Argument #2. The input and output file formats are specified in Appendix A. See Notes 3, 4 and 5. Issues software generated clock pulse to HSP45116-DB by toggling the CTL0 bit in the HSP-EVAL's CTL0-15 Register. See Note 4. Reads data on the HSP45116-DB's RO0-15 and IO0-15 outputs and prints data to screen. See Note 4 and 5. Displays signal mapping between the CTL Control Register and the HSP45116 control inputs (assumes default jumper configuration shown in Table 1). Displays current state of CTL Control Register. Displays the printer port and HSP-EVAL board address that the NCOM_CMD program is using for communication between the PC and the HSP-EVAL. The HSPEVAL board address is set by inserting a jumper in the ADDR0-7 positions of it's J4 Jumper Field. PORT NUMBER (1-3) BOARD ADDRESS (0-7) Change The Printer Port And HSP-EVAL Board Address that the NCOM_CMD Program is using for communication between the PC and the HSP-EVAL to those specified in Arguments 1 and 2. The HSP-EVAL Board Address is set by inserting a Jumper in the ADDR0-7 positions of it's J4 Jumper Field. List available commands together with a brief description. CK RD SM CR PC P# ? NOTES: 1. The CF, OF, TI commands load the specified 32-bit value into the HSP45116's MS and LS input registers. After the configuration data has been loaded into the MS and LS Registers, the corresponding enable, ENCFREG, ENOFREG, or ENTIREG is asserted. The enable signal is then registered on chip by a single software generated clock provided a jumper is inserted at the CTL0 position of the J4 jumper field on the HSP-EVAL. Otherwise, it is assumed that the selected clock source is fast enough to register the enable signal prior to a subsequent load of one of another 32bit configuration register. The register enables, ENCFREG, ENOFREG, and ENTIREG must be jumpered to the CTL Control Bus as in the default configuration shown in Table 1. 2. When commands are issued to load registers internal to the HSP45116, it is assumed that the microprocessor interface signals, WR and A0-1 are jumpered to the CTL0-15 bus as in the default configuration shown in Table 1. 3. If the complex input buses of the HSP45116-DB are to be driven by the HSP-EVAL's Input Registers 1 and 2, their outputs must be enabled by placing jumpers in the OE_BUS1 and OE_BUS2 positions of the J4 jumper field on the HSP-EVAL. 4. This command is only valid if a software generated clock source has been selected by inserting a jumper in the CTL0 position of the HSP-EVAL's J4 jumper field. 5. Commands required to read data on the HSP45116-DB's complex outputs only function properly if the output of the shift register is selected for reading by inserting a jumper in the SR_RD position of the HSP-EVAL's J4 jumper field. The Command specifies 1 of 14 actions to be taken, and the Arguments (ARG1, ARG2) represent additional data required by the command. For example, the HSP45116's Center Frequency Register would be loaded with a value of 40000000(HEX) by typing: NCOM_CMD CF 40000000 is an example of how the Command Line program might be used in a DOS batch file. Signal Headers The HSP45116-DB maps the NCOM's inputs and outputs to three 50-pin signal headers, J1-J3. The signal headers are used to connect the NCOM's I/O and control pins to the HSP-EVAL's I/O and control busses through three 50 position connectors. The Control Panel and Command Line interface software control the operation of the HSP45116-DB by up or down loading data to registers on-board the HSPEVAL which drive or monitor the I/O and control busses. The J1 Input Header maps two 16-bit busses to the real and imaginary inputs of the HSP45116, RIN0-15 and IMIN0-15. In addition, a bidirectional clock line is routed to this header as shown by the signal map in Table 3. When mated with the J1 connector on the HSP-EVAL, the HSP45116's real and imaginary inputs map to the HSP-EVAL's Input Bus 2 and 1, IN2_0-15 and IN1_0-15, respectively. 8 HSP45116-DB TABLE 3. SIGNAL ASSIGNMENTS FOR 50 POSITION INPUT CONNECTOR J1 PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 J1A SIGNAL MNEMONIC N.C. RIN0 RIN2 RIN4 RIN6 GND RIN9 RIN11 RIN134 RIN15 N.C. IMIN1 IMIN3 IMIN5 IMIN7 IMIN8 IMIN10 IMIN12 IMIN14 GND GND GND GND GND GND J1B SIGNAL MNEMONIC GND RIN1 RIN3 RIN5 RIN7 RIN8 RIN10 RIN12 RIN14 GND IMIN0 IMIN2 IMIN4 IMIN6 GND IMIN9 IMIN11 IMIN13 IMIN15 CLKIN N.C. VCC VCC VCC VCC TABLE 4. SIGNAL ASSIGNMENTS FOR 50 POSITION OUTPUT CONNECTOR J2 PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 J2A SIGNAL MNEMONIC OER RO0 RO2 RO4 RO6 GND RO9 RO11 RO13 RO15 OEI IO1 IO3 IO5 IO7 IO8 IO10 IO12 IO14 GND GND GND GND GND GND J2B SIGNAL MNEMONIC GND RO1 RO3 RO5 RO7 RO8 RO10 RO12 RO14 GND IO0 IO2 IO4 IO6 GND IO9 IO11 IO13 IO15 CLKOUT TICO PACO N.C. N.C. N.C. The J2 Output Header maps two 16-bit busses to the real and imaginary outputs of the HSP45116, RO0-15 and IO015. In addition, two HSP45116 status outputs, PACO and TICO, two HSP45116 output enables, OER and OE, and a bidirectional clock line are routed to this header as shown by the signal map in Table 4. When mated with the J2 connector on the HSP-EVAL, the HSP45116's real and imaginary outputs map to the HSP-EVAL's Output Bus 2 and 1, OUT2_0-15 and OUT1_0-15, respectively. The J3 Control Header maps one 16-bit bus to the HSP45116's control input, C0-15, and provides jumper positions for the Configuration Jumper Fields that flank the header. When mated with the HSP-EVAL's J3 Control Connector the HSP45116's Control Inputs, C0-15, are mapped to the HSP-EVAL's Input Bus 3, IN3_0-15, and the jumper positions are mapped the HSP-EVAL's Control Bus, CTL0-15. The signal map for the J3 Control Header is shown in Table 1. Configuration Jumper Field The Configuration Jumper Fields A and B flank either side of the Control Header J3 as shown in Table 1. Positions within the Jumper Field's SA and SB signal rows map to various HSP45116 control inputs. The control inputs may be jumpered to ground or the HSP-EVAL's CTL4-15 bus via the J3 Control Header. If a control signal mapped to SA and SB is not jumpered to GND or CTL4-15, the signal is pulled high. The Configuration Jumper Field A is also used to select whether the HSP45116's clock source is provided through the J1 Input Header or the J2 Output Header. If jumpers are inserted as shown in Figure 5, a clock signal supplied through the CLK_IN pin of the J1 Input Header drives a buffer whose output clocks the HSP45116. The jumper inserted between JA1 and JA2 feeds the buffered clock signal to the CLK_OUT pin of the J2 Output Header. If jumpers are inserted as shown in Figure 6, the CLK_OUT pin of the J2 Output Connector drives the clock buffer which 9 HSP45116-DB in turn drives the clock input of the HSP45116. The jumper inserted between JA2 and SA2 allows the Input Header's CLK_IN pin to be driven by the buffer output. NOTE: The jumper placement shown in Figure 5 is the standard configuration.. J3A SA Appendix A Data File Structures The Input/Output data files used by the HSP45116-DB Control Panel and Command Line Interface software contain complex data samples. The data files consist of a seven line header followed by the data itself. The header section must follow this format: Line 1: Line 2: Line 3: Comment #1 Comment #2 Comment #3 Comment #4 Comment #6 c1n 1 JA FIGURE 5. JUMPER CONFIGURATION IF CLOCK IS SUPPLIED THROUGH J1 INPUT HEADER J3A Line 4: Line 5: SA JA Line 7: 1 (Real Component) (Imaginary Component) * * FIGURE 6. JUMPER CONFIGURATION IF CLOCK IS SUPPLIED THROUGH J2 OUTPUT HEADER * The `n' on the 7th line of the header should be replaced by the number of complex samples in the file. Following the header, the complex samples are listed one per row with the real part listed first followed by the complex part. The real and imaginary components of the complex data sample are represented as 16-bit two's complement values. As a result, the real and imaginary parts of the data sample are integer values bounded by 32767 and -32768. The CMPRFILE installed in the NCOM_CHK subdirectory is an example of the input data file structure. The HSP45116-DB is shipped from the factory with the default jumper configuration shown by the overlay of heavy lines onto the signal map in Table 1. For the Control Panel and Command Line Interface software to properly control operation of the HSP45116, it is assumed that the HSP45116 control inputs are jumpered as specified in the default configuration. Also, the system test software, NCOM_CHK, must be run using the default configuration. 10 VCC OER J1B J2A J2B J1A TICO RIN0 RIN2 RIN4 RIN6 RO0 RO2 RO4 RO6 OEI RO9 RO11 RO13 RO15 IO0 IO2 IO4 IO6 C4 0.01F C3 0.01F C2 0.01F C1 0.01F IO9 IO11 IO13 IO15 CKOUT VCC RIN9 RIN11 RIN13 RIN15 IMIN0 IMIN2 IMIN4 IMIN6 IMIN9 IMIN11 IMIN13 IMIN15 CKIN IO1 IO3 IO5 IO7 IO8 IO10 IO12 IO14 RO1 RO3 RO5 RO7 RO8 RO10 RO12 RO14 RIN1 RIN3 RIN5 RIN7 RIN8 RIN10 RIN12 RIN14 PACO 11 IMIN1 IMIN3 IMIN5 IMIN7 IMIN8 IMIN10 IMIN12 IMIN14 U1A 3 74AC86 U1B 6 74AC86 U1C 9 10 CKIN C0 C2 C4 C6 CKOUT SA JA J3A J3B JB SB C[0..15] NCOMCK C9 C11 C13 C15 C1 C3 C5 C7 C8 C10 C12 C14 CTL0 CTL2 CTL4 CTL6 CTL1 CTL3 CTL5 CTL7 CTL8 CTL10 CTL12 CTL14 CTL9 CTL11 CTL13 CTL15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 0 9 8 76 5 4 32 Z8 1 VCC U1D 12 13 11 1 74AC86 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 C5 0.01F RIN[0..15] IMIN[0..15] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 IO[0..15] RO[0..15] 1 2 HSP45116-DB 4 5 VCC VCC ENTIREG 8 GND 74AC86 ENPHREG ENOFREG ENCFREG BINFMT AD0 WR ACC MOD0 MOD1 ENI CLROFR LOAD PMSEL AD1 MUX0 MUX1 PACI PEAK RBYTILD MODPI/2PI 1 0 9 8 76 5 4 32 1 0 9 8 76 5 4 32 Z9 VCC Z7 1 Z1 2 3 4 5 6 7 8 9 10 RIN8 RIN9 RIN10 RIN11 RIN12 RIN13 RIN14 RIN15 1 2 3 4 5 6 7 8 9 10 1 Z2 RIN0 RIN1 RIN2 RIN3 RIN4 RIN5 RIN6 RIN7 12 Z3 1 1 Z4 2 3 4 5 6 7 8 9 10 U2 HSP45116 IMIN8 2 IMIN9 3 IMIN10 4 IMIN11 5 IMIN12 6 IMIN13 7 IMIN14 8 IMIN15 9 10 Z5 1 CIN8 CIN9 CIN10 CIN11 CIN12 CIN13 CIN14 CIN15 1 Z6 IMIN0 IMIN1 IMIN2 IMIN3 IMIN4 IMIN5 IMIN6 IMIN7 IMIN8 IMIN9 IMIN10 IMIN11 IMIN12 IMIN13 IMIN14 IMIN15 IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO13 IO14 IO15 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 D3 B2 C3 C4 A2 B3 C5 B4 A3 A4 B5 A5 C6 B6 B7 A6 A7 C7 C8 IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO13 IO14 IO15 IO16 IO17 IO18 IO19 PACO TICO DET0 DET1 L13 P1 N15 L14 E13 C14 B15 D13 C13 B14 C12 B13 B12 C11 A13 B11 A12 C10 B10 A11 B9 C9 A10 B8 IMIN0 IMIN1 IMIN2 IMIN3 IMIN4 IMIN5 IMIN6 IMIN7 IMIN8 IMIN9 IMIN10 IMIN11 IMIN12 IMIN13 IMIN14 IMIN15 IMIN16 IMIN17 IMIN18 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 Q14 P13 N11 P12 Q13 Q12 P11 Q11 N10 P10 P9 Q10 Q9 N9 N8 P8 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 N7 P7 Q5 Q6 N3 M3 N13 N12 ADR0 ADR1 EEE CLK NNNE WR P OCN MOD0 HF F P MOD1 RRRH OUTMUX0 C E E E A OUTMUX1 S G G G C E N T I RE EN GI M O D R PC B I L PY / R L MT 2 OOS I PF AEL I RDL D P ASSA CHHC I 01C B OO I EE NP R I F E OE OE MA E X E X T KRT I T P MN N QP QN P N P L P L K L N MP MMN 6115354644332132221111 4344 RIN[0..15] RIN0 RIN1 RIN2 RIN3 RIN4 RIN5 RIN6 RIN7 RIN8 RIN9 RIN10 RIN11 RIN12 RIN13 RIN14 RIN15 K2 J2 K1 J1 J3 H3 H2 F1 G3 G2 E1 F2 F3 D1 E2 C1 E3 D2 C2 RO[0..15] IMIN0 IMIN1 IMIN2 IMIN3 IMIN4 IMIN5 IMIN6 IMIN7 RIN0 RIN1 RIN2 RIN3 RIN4 RIN5 RIN6 RIN7 RIN8 RIN9 RIN10 RIN11 RIN12 RIN13 RIN14 RIN15 RIN16 RIN17 RIN18 RO0 RO1 RO2 RO3 RO4 RO5 RO6 RO7 RO8 RO9 RO10 RO11 RO12 RO13 RO14 RO15 RO16 RO17 RO18 RO19 RO0 RO1 RO2 RO3 RO4 RO5 RO6 RO7 RO8 RO9 RO10 RO11 RO12 RO13 RO14 RO15 M15 K13 K14 L15 J14 J13 K15 H14 H13 G13 G15 F15 G14 F14 F13 E15 E14 D15 C15 D14 IMIN[0..15] CIN0 CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 IO[0..15] C[0..15] HSP45116-DB PACO TICO VCC VCC GND GND AD0 AD1 NCOMCK WR MOD0 MOD1 MUX0 MUX1 ENPHREG ENOFREG ENCFREG ENTIREG ENI MODPI/2PI CLROFR LOAD PMSEL RBYTILD PACI ACC BINFMT PEAK OER OEI HSP45116-DB HSP-EVAL Limited Warranty Intersil warrants the HSP-EVAL to be free of defects in material and workmanship under normal use for a period of ninety (90) days. Intersil also warrants that the HSP-EVAL User's Manual is substantially complete and contains all the information which Intersil considers necessary to use the HSP-EVAL, and that the HSP-EVAL functions substantially as described in the HSP-EVAL User's Manual. Intersil will replace the HSP-EVAL as Intersil's sole duty under this warranty only if you ship it, postage prepaid, to Intersil within ninety (90) days of such acquisition and provide proof of date of acquisition. This limited warranty does not extend to any products which have been damaged as a result of accident, misuse, abuse, or as a result of service or modification by anyone other than Intersil or Intersil's authorized representatives. Intersil makes no other express or implied warranty with respect to the HSP-EVAL other than the limited warranty set forth above. Intersil disclaims all implied warranties of merchantability and/or fitness for a particular purpose. In any event, all implied warranties shall be limited to the duration of this warranty. The liability of Intersil, if any, shall under any tort, contract or other legal theory be limited to the actual price paid for such product and shall in no event include incidental, consequential, special or indirect damages of any kind, even if Intersil is aware of the possibility of such damages. Intersil reserves the right to revise and make changes to this manual and the HSP-EVAL from time to time without obligation to notify any person of, or to provide any person with, such revisions or changes. HSP45116-DB Software License Agreement In return for the purchase price of the HSP45116-DB product, the Purchaser receives from Intersil Corporation ("Intersil") a non-exclusive nontransferable (except as set for below) license under Intersil copyrights to use the software subject to the following terms and conditions: [1] The Software is protected by both United States Copyright Law and International Treaty provisions. Therefore, you must treat the Software like any other copyrighted material (e.g. a book) and may not copy, distribute or make derivatives of any part thereof except that you may either a) make one copy of the Software solely for archival purposes, or b) transfer the Software to a single hard disk provided you keep the original solely for backup or archival purposes. [2] The Software may be transferred to a third party on a permanent basis provided you retain no copies and the recipient agrees, in writing to Intersil, to the terms of this Agreement. [3] If the software package contains both 3.5" and 5.25" disks, then you may use only the disks appropriate for your single-user computer. You may not use the other disks on another computer or loan, rent, lease, or transfer them to another user except as part of the permanent transfer (as provided above) of all Software. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 13 |
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